Pilot-to-Production: Chips JU Pilot Lines
KIIP also provides access to the first five open-access pilot lines of Chips JU, enabling companies, research institutions, and start-ups to prototype and scale innovative semiconductor solutions. The Chips Joint Undertaking (Chips JU) has launched five open-access pilot lines across Europe to enable prototyping, R&D, testing, and early manufacturing of next-generation semiconductor technologies. These facilities are part of the Chips for Europe Initiative under the EU Chips Act.
Available Pilot Lines
NanoIC — Beyond-2 nm Leading-Edge System-on-Chip
What it is: A pilot line enabling state-of-the-art CMOS technologies beyond the 2 nm node for advanced SoC development, targeting logic, memory, and interconnect innovation.
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FAMES — Fully Depleted SOI Applications
What it is: Pilot line focused on FD-SOI technology with a roadmap to low-power, high-performance semiconductor solutions including embedded memories, RF, and 3D integration.
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APECS — Advanced Packaging & Heterogeneous Integration
What it is: Pilot line for advanced packaging, chiplet integration and heterogeneous system technologies, coordinated by a Fraunhofer-led consortium.
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WBG — Wide Bandgap Materials (SiC & GaN)
What it is: Pilot line developing wide bandgap semiconductor devices (such as SiC and GaN) for high-performance power and RF electronics applications.
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PIXEurope — Photonic Integrated Circuits
What it is: A pilot line initiative to build an open-access photonic integrated circuits (PIC) ecosystem, covering design, fabrication, integration, testing and reliability technologies.
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These pilot lines, available via Chips JU and supported by KIIP, help bridge the gap between research-level design and industrial-scale manufacturing. They offer the infrastructure and expertise to validate and scale novel semiconductor technologies under open, non-discriminatory access.