{"id":2791,"date":"2025-08-19T15:33:10","date_gmt":"2025-08-19T12:33:10","guid":{"rendered":"https:\/\/kiip.ee\/vabavaralised-ja-tasuta-tooriistad-kiipide-disainimiseks-ja-testimiseks\/"},"modified":"2026-04-28T12:27:55","modified_gmt":"2026-04-28T09:27:55","slug":"tools","status":"publish","type":"page","link":"https:\/\/kiip.ee\/en\/tools\/","title":{"rendered":"Open source and free tools for chip design and testing"},"content":{"rendered":"\n
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Schematic Capture & PCB Design<\/strong><\/h3>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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KiCad<\/h3>\n\n\n\n

An open-source suite for electronic design automation (EDA), facilitating schematic capture and PCB layout.<\/p>\n\n\n\n

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See more<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
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gEDA<\/h3>\n\n\n\n

A collection of tools for electrical circuit design, simulation, and prototyping.<\/p>\n\n\n\n

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Horizon EDA<\/h3>\n\n\n\n

A modern EDA tool for schematic capture and PCB layout, emphasizing a streamlined user experience.<\/p>\n\n\n\n

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Fritzing<\/h3>\n\n\n\n

Designed to help designers and artists work creatively with interactive electronics, offering schematic capture and PCB layout functionalities.<\/p>\n\n\n\n

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Simulation & Modeling<\/strong><\/h3>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Ngspice<\/h3>\n\n\n\n

An open-source mixed-level\/mixed-signal electronic circuit simulator.<\/p>\n\n\n\n

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Verilator<\/h3>\n\n\n\n

A tool that converts Verilog code into C++ or SystemC code for simulation purposes.<\/p>\n\n\n\n

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GHDL<\/h3>\n\n\n\n

An open-source simulator for VHDL, allowing for compilation and simulation of VHDL designs.<\/p>\n\n\n\n

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Qucs<\/h3>\n\n\n\n

Stands for Quite Universal Circuit Simulator; it’s a circuit simulator with a graphical user interface.<\/p>\n\n\n\n

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HDL Synthesis & Simulation<\/strong><\/h3>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Yosys<\/h3>\n\n\n\n

An open-source framework for RTL synthesis supporting Verilog-2005.<\/p>\n\n\n\n

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Icarus Verilog<\/h3>\n\n\n\n

A Verilog simulation and synthesis tool.<\/p>\n\n\n\n

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GHDL<\/h3>\n\n\n\n

As mentioned, also serves for VHDL synthesis and simulation.<\/p>\n\n\n\n

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ASIC Design Flows<\/strong><\/h3>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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OpenLane<\/h3>\n\n\n\n

An automated RTL to GDSII flow, built around open-source tools, for digital ASIC design.<\/p>\n\n\n\n

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OpenROAD<\/h3>\n\n\n\n

Aims to develop a fully autonomous, open-source RTL-to-GDS flow for digital SoC design.<\/p>\n\n\n\n

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SiliconCompiler<\/h3>\n\n\n\n

A Python-based framework to create custom chip design flows.<\/p>\n\n\n\n

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Coriolis2<\/h3>\n\n\n\n

A tool for digital ASIC design, focusing on the backend (place and route).<\/p>\n\n\n\n

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OPUS<\/h3>\n\n\n\n

A platform for analog and mixed signal optimization<\/p>\n\n\n\n

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Verification & Formal Methods<\/strong><\/h2>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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OpenSTA<\/h3>\n\n\n\n

A tool for static timing analysis of digital circuits.<\/p>\n\n\n\n

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OpenTimer<\/h3>\n\n\n\n

A high-performance timing analysis tool for large-scale digital designs.<\/p>\n\n\n\n

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See more<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
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Verible<\/h3>\n\n\n\n

A suite of SystemVerilog developer tools, including a parser, formatter, and lint tool.<\/p>\n\n\n\n

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Surelog<\/h3>\n\n\n\n

A SystemVerilog preprocessor, parser, and elaborator.<\/p>\n\n\n\n

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UHDM<\/h3>\n\n\n\n

Stands for Universal Hardware Data Model; it provides a standardized data model for SystemVerilog.<\/p>\n\n\n\n

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NuSMV<\/h3>\n\n\n\n

A symbolic model checker for the verification of finite state systems.<\/p>\n\n\n\n

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Test & Debug<\/strong><\/h3>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n
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GTKWave<\/h3>\n\n\n\n

A waveform viewer for VCD (Value Change Dump) files, useful for debugging digital designs.<\/p>\n\n\n\n

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See more<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
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AutoBench<\/h3>\n\n\n\n

An automatic testbench generation tool using large language models for HDL design.<\/p>\n\n\n\n

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See more<\/a><\/div>\n<\/div>\n<\/div>\n\n\n\n
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edaplayground<\/h3>\n\n\n\n

An online platform to run and share HDL code, supporting various simulators.<\/p>\n\n\n\n

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See more<\/a><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

Schematic Capture & PCB Design KiCad An open-source suite for electronic design automation (EDA), facilitating schematic capture and PCB layout. gEDA A collection of tools for electrical circuit design, simulation, and prototyping. Horizon EDA A modern EDA tool for schematic capture and PCB layout, emphasizing a streamlined user experience. Fritzing Designed to help designers and […]<\/p>\n","protected":false},"author":7,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-2791","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/pages\/2791","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/users\/7"}],"replies":[{"embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/comments?post=2791"}],"version-history":[{"count":12,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/pages\/2791\/revisions"}],"predecessor-version":[{"id":3506,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/pages\/2791\/revisions\/3506"}],"wp:attachment":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/media?parent=2791"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}