{"id":3543,"date":"2026-09-08T15:30:59","date_gmt":"2026-09-08T12:30:59","guid":{"rendered":"https:\/\/kiip.ee\/?p=3543"},"modified":"2026-09-08T15:31:00","modified_gmt":"2026-09-08T12:31:00","slug":"interconnect-is-the-bottleneck-takeaways-from-chiplet-summit-2026","status":"publish","type":"post","link":"https:\/\/kiip.ee\/en\/interconnect-is-the-bottleneck-takeaways-from-chiplet-summit-2026\/","title":{"rendered":"Interconnect Is the Bottleneck: Takeaways from Chiplet Summit 2026"},"content":{"rendered":"\n

We had the pleasure to attend the Chiplet Summit 2026 to follow the latest developments in chiplet technologies and assess their relevance for competence building and future applications in Estonia.<\/strong><\/p>\n\n\n\n

The summit brings together EDA vendors, foundry and OSAT engineers, AI accelerator companies and standards bodies, providing a useful view of where the industry stands in practical terms.<\/p>\n\n\n\n

Interconnect is the bottleneck<\/strong><\/h6>\n\n\n\n

One message was repeated across many of the summit sessions: interconnect is the bottleneck. Compute density continues to improve, while the bandwidth needed to feed that compute, both across die-to-die (D2D) links and out of the package, is not keeping pace. The gap is widening rather than closing.<\/p>\n\n\n\n

The scale of the challenge was illustrated in one presentation through projections for AI data centres. The total addressable market for AI data-centre xPUs and networking was estimated at approximately USD 160\u2013210 billion in 2024, rising to USD 420\u2013585 billion by 2030. At the same time, the associated power requirement was projected to grow from around 60 GW to approximately 240 GW. The conclusion presented was that data-centre expansion is becoming power-limited rather than demand-limited, with system-level connectivity making the difference between scaling and stalling.<\/p>\n\n\n\n

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The datacentre problem restated as a power problem. Four times the money, four times the gigawatts.<\/em><\/figcaption><\/figure>\n\n\n\n

Rebellions<\/strong>, the Korean AI accelerator company, presented Rebel 100: four NPU dies in a 2.5D package using Samsung I-CubeS, which the company described as a CoWoS-S equivalent. UCIe-Advanced links provide 1 TB\/s full-duplex bandwidth between the NPUs, while HBM3E provides 1.2 TB\/s per stack.<\/p>\n\n\n\n

The presentation focused not only on the product but also on the experience of bringing the design to silicon. Power integrity was addressed by hierarchically staggering the activation of neural cores to reduce rapid changes in current demand. Measurements on silicon showed a reduction of more than 20 mV peak-to-peak in noise. An integrated silicon capacitor die positioned next to the HBM is used to flatten peaks in power-distribution-network impedance, while a control loop combining a voltage-droop detector and thermal sensor can reduce the clock frequency before operating conditions become critical.<\/p>\n\n\n\n

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Rebel 100 topology: four NPUs, UCIe-Advanced between them, HBM3E on the edges, integrated silicon capacitors (ISC) in the corners.<\/em><\/figcaption><\/figure>\n\n\n\n
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Staggered core activation, simulated on the left and measured on the right. This is the kind of detail that only shows up once you have real silicon.<\/em><\/figcaption><\/figure>\n\n\n\n

Rebellions also presented a benchmark showing 1.9 times more tokens per watt than an NVIDIA H200 PCIe card when running Llama 3.3 70B, with both operating at 600 W in a single-card, single-batch W8A16 configuration. Mellik notes that vendor benchmarks should be treated with the usual caution. Regardless of the exact multiplier, the broader point remains: a mid-sized, well-funded design house is shipping a multi-die AI product. Chiplet-based architectures are no longer limited to hyperscalers.<\/p>\n\n\n\n

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The comparison everyone photographed. Single-card, same TDP.<\/em><\/figcaption><\/figure>\n\n\n\n

Another perspective came from Lightmatter.<\/strong> Steve Klinger, VP of Product, presented 3D-stacked photonic interconnect in a talk titled \u201cOvercoming AI Scaling Barriers with Light\u201d. The figures presented were on the order of 100 Gb\/s per wavelength and approximately 1.6 Tb\/s per fibre. With around one hundred fibres coupled to a single photonic interposer, aggregate bandwidth could reach the order of 100 Tb\/s from one package.<\/p>\n\n\n\n

We remain cautious about the timeline, noting that photonics has been expected to be \u201ctwo years away\u201d for around fifteen years. However, his main conclusion from the presentation is that electrical D2D links do not currently have a roadmap reaching anywhere near those bandwidth figures.<\/p>\n\n\n\n

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From one of the tutorials: WDM basics. Microring modulators sitting along a single bus waveguide, no mux\/demux needed. Useful background for why the photonic numbers scale the way they do.<\/em><\/figcaption><\/figure>\n\n\n\n

The practical takeaway for multi-die architecture is to start from the interconnect budget and work backwards, rather than beginning with the compute blocks.<\/p>\n\n\n\n

D2D verification increasingly depends on simulation and emulation<\/strong><\/h6>\n\n\n\n

A second major theme was the tooling required to verify die-to-die connections.<\/p>\n\n\n\n

Dr Subramanian Lalgudi of Siemens <\/strong>EDA presented a Veloce emulation use case alongside the Calibre 3DStack flow and, importantly, 3D thermal analysis. Keysight addressed measurement and D2D characterisation. Built-in self-test (BIST) for D2D links was also discussed repeatedly as a practical answer to the challenge of verifying a link that cannot be directly probed.<\/p>\n\n\n\n

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Siemens EDA on D2D interface planning. The title says “fast, robust and scalable”; the content was mostly about not needing a second tape-out.<\/em><\/figcaption><\/figure>\n\n\n\n

The UCIe 2.0 session highlighted why this matters. Micro-bumps cannot be probed directly. Testing therefore has to be carried out through other connections, such as JTAG or the UCIe sideband. For chiplets without package pins, access may need to be provided through a neighbouring die.<\/p>\n\n\n\n

Rebellions presented similar lessons from the perspective of bringing up a multi-die product. Backup channels such as QSPI, I2C and JTAG are needed to retain command and control when the main NoC or UCIe link is unavailable. Direct JTAG paths that bypass the SoC fabric support early die validation, while as much bring-up as possible can be carried out using an emulator before silicon becomes available.<\/p>\n\n\n\n

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UCIe 2.0 on test, debug and manageability. The first bullet is the whole argument<\/em>.<\/figcaption><\/figure>\n\n\n\n
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Rebellions’ lessons learned. “Independent lifeline” is a good name for it.<\/em><\/figcaption><\/figure>\n\n\n\n

Physical packages are unlikely to be built solely to test a D2D interconnect. Given the cost and lead time of advanced packaging, simulation and emulation are essential for first-pass success.

Thermal behaviour is another important part of the challenge. Mellik notes that it is still underestimated by many teams: when dies are stacked vertically, heat becomes an architectural rather than simply a manageable thermal issue. The 3D IC design flow presented by Siemens illustrated the range of disciplines involved, including thermal behaviour, stress, design for test, photonics layout and mechanical co-design.<\/p>\n\n\n\n

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Siemens’ view of what a 3D IC flow now touches: thermal, stress, DFT, photonics layout, mechanical co-design. Twelve tools around one integrator says something about how many disciplines have to agree before tape-out.<\/em><\/figcaption><\/figure>\n\n\n\n
Standards versus customisation<\/strong><\/h6>\n\n\n\n

UCIe is the obvious standard for D2D communication, and the UCIe Consortium delivered one of the summit keynotes. However, Mellik found the discussions outside the keynote more nuanced: in practice, standards are currently outweighed by customisation.<\/p>\n\n\n\n

Leading-edge designs tune the interface, bump map, PHY and packaging to the requirements of the specific product. Compliance with the standard remains a goal, but it is rarely the binding constraint.<\/p>\n\n\n\n

Qualcomm\u2019s chiplet presentation illustrated this balance. Its offering included electrical I\/O chiplets, optical I\/O chiplets, a custom I\/O chiplet with a customised SerDes count and a specific memory interface, as well as extended UCIe 2D\/3D options. As Mellik observed, the word \u201ccustom\u201d appeared on the slide more often than the word \u201cstandard\u201d.<\/p>\n\n\n\n

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Qualcomm’s chiplet offering. Note the third column.<\/em><\/figcaption><\/figure>\n\n\n\n

This also matters for the idea of an Open Chiplet Marketplace<\/strong>, where compatible chiplets from different suppliers could be selected and assembled into a system. The Open Compute Project is working towards this goal, and Andres Mellik, the Program Manager for the Estonian Chips Competence Center, considers the ambition genuine.<\/p>\n\n\n\n

However, electrical interfaces are only one part of the interoperability challenge. Bump maps, testing, thermal characteristics and mechanical interfaces also need to be standardised and enforced. Until then, Mellik sees the marketplace as closer to a catalogue of components that can be made to work together through custom integration than to plug-and-play procurement: worth watching, but not yet a procurement strategy.<\/p>\n\n\n\n

Agentic AI is entering the design flow<\/strong><\/h6>\n\n\n\n

The major EDA keynotes on the second day also addressed agentic AI in semiconductor design.<\/p>\n\n\n\n

One presentation used an autonomy scale similar to that applied to self-driving vehicles, ranging from L1 assistance to L5 full autonomy, and placed current tools at approximately L2 to L3. Among the capabilities presented for the future were autonomously partitioning a multi-die design and autonomously designing a multi-die power network.<\/p>\n\n\n\n

We\u2019d like to point out that these are precisely two of the tasks in a multi-die project that currently require some of the most experienced engineers.<\/p>\n\n\n\n

He is not yet convinced that such tasks can be automated to the extent envisaged, but neither does he dismiss the possibility. The fact that these capabilities were presented in major EDA keynotes rather than side sessions is, in his view, an indication of where vendors are directing their R&D investment.<\/p>\n\n\n\n

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The autonomy ladder, chip-design edition.<\/em><\/figcaption><\/figure>\n\n\n\n
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The wish list. Partitioning and power network design are the ones to watch.<\/em><\/figcaption><\/figure>\n\n\n\n
Advanced packaging is a capability Europe needs to understand<\/strong><\/h6>\n\n\n\n

One of our main conclusions from the summit concerns the advanced packaging landscape.<\/p>\n\n\n\n

A tutorial presented the leading-edge packaging options by vendor: TSMC with SoIC, CoWoS-S, CoWoS-R and CoWoS-L; Intel with Foveros, Foveros Direct and EMIB; and Samsung with X-Cube, SAINT and I-Cube.<\/p>\n\n\n\n

The list is short, as leading-edge packaging capacity and know-how are concentrated among a small number of companies, and those controlling the capacity and expertise have considerable leverage.<\/p>\n\n\n\n

For those working on chip-related competence building in Europe, we see this as a gap that needs to be understood before focusing the discussion on process nodes. Mapping the advanced packaging landscape is therefore one of the key areas he identifies for further attention.<\/p>\n\n\n\n

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The packaging menu. Short list.<\/em><\/figcaption><\/figure>\n\n\n\n
Chiplets could also have a role in medical wearables<\/strong><\/h6>\n\n\n\n

Much of Chiplet Summit was focused on AI accelerators and data centres. The market data presented at the summit reflected this: of the chiplet design starts recorded for 2023\u20132024, data-centre AI accounted for 30%, edge inference for 22%, automotive for 18%, high-performance computing for 15% and consumer applications for 12%. Medical applications did not appear in the breakdown.<\/p>\n\n\n\n

We see the potential for chiplets in medical wearables, where the same modular logic could be applied at the other end of the power spectrum. A wearable medical device may need a mixed-signal front end, ultra-low-power computing, wireless communication and sensing that may be better suited to a different process than digital CMOS, such as photonics for optical biosensing.<\/p>\n\n\n\n

Today, these functions may be implemented either in a single system-on-chip with compromises or through multiple discrete components on a circuit board. A chiplet-based architecture could instead combine a mixed-signal die, an ultra-low-power compute die, a communication die and a CMOS or photonic sensing die within a single package.<\/p>\n\n\n\n

Such an architecture is exactly the kind of heterogeneous integration that the chiplet ecosystem is being built to support. Medical wearables were not discussed at the summit, which Mellik considers an indication that the area may offer an opportunity worth exploring.<\/p>\n\n\n\n

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Where the design starts are going. Note what is missing from the list.<\/em><\/figcaption><\/figure>\n\n\n\n

Andres Mellik attended Chiplet Summit 2026, held on 17\u201319 February at the Santa Clara Convention Center in California. The next Chiplet Summit is scheduled for 30 March\u20131 April 2027, again in Santa Clara.<\/strong><\/p>\n\n\n\n

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We had the pleasure to attend the Chiplet Summit 2026 to follow the latest developments in chiplet technologies and assess their relevance for competence building and future applications in Estonia. The summit brings together EDA vendors, foundry and OSAT engineers, AI accelerator companies and standards bodies, providing a useful view of where the industry stands […]<\/p>\n","protected":false},"author":17,"featured_media":3544,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[20,23],"tags":[],"class_list":["post-3543","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-article","category-news"],"acf":[],"_links":{"self":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/posts\/3543","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/users\/17"}],"replies":[{"embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/comments?post=3543"}],"version-history":[{"count":2,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/posts\/3543\/revisions"}],"predecessor-version":[{"id":3575,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/posts\/3543\/revisions\/3575"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/media\/3544"}],"wp:attachment":[{"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/media?parent=3543"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/categories?post=3543"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/kiip.ee\/en\/wp-json\/wp\/v2\/tags?post=3543"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}