Schematic Capture & PCB Design
KiCad
An open-source suite for electronic design automation (EDA), facilitating schematic capture and PCB layout.
gEDA
A collection of tools for electrical circuit design, simulation, and prototyping.
Horizon EDA
A modern EDA tool for schematic capture and PCB layout, emphasizing a streamlined user experience.
Fritzing
Designed to help designers and artists work creatively with interactive electronics, offering schematic capture and PCB layout functionalities.
Simulation & Modeling
Ngspice
An open-source mixed-level/mixed-signal electronic circuit simulator.
Verilator
A tool that converts Verilog code into C++ or SystemC code for simulation purposes.
GHDL
An open-source simulator for VHDL, allowing for compilation and simulation of VHDL designs.
Qucs
Stands for Quite Universal Circuit Simulator; it’s a circuit simulator with a graphical user interface.
HDL Synthesis & Simulation
Yosys
An open-source framework for RTL synthesis supporting Verilog-2005.
Icarus Verilog
A Verilog simulation and synthesis tool.
GHDL
As mentioned, also serves for VHDL synthesis and simulation.
ASIC Design Flows
OpenLane
An automated RTL to GDSII flow, built around open-source tools, for digital ASIC design.
OpenROAD
Aims to develop a fully autonomous, open-source RTL-to-GDS flow for digital SoC design.
SiliconCompiler
A Python-based framework to create custom chip design flows.
Coriolis2
A tool for digital ASIC design, focusing on the backend (place and route).
Verification & Formal Methods
OpenSTA
A tool for static timing analysis of digital circuits.
OpenTimer
A high-performance timing analysis tool for large-scale digital designs.
Verible
A suite of SystemVerilog developer tools, including a parser, formatter, and lint tool.
Surelog
A SystemVerilog preprocessor, parser, and elaborator.
UHDM
Stands for Universal Hardware Data Model; it provides a standardized data model for SystemVerilog.
NuSMV
A symbolic model checker for the verification of finite state systems.
Test & Debug
GTKWave
A waveform viewer for VCD (Value Change Dump) files, useful for debugging digital designs.
AutoBench
An automatic testbench generation tool using large language models for HDL design.
edaplayground
An online platform to run and share HDL code, supporting various simulators.